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Authors
Affiliations
1 SSGI, Bhilai, IN
Source
Digital Signal Processing, Vol 8, No 4 (2016), Pagination: 98-102
Abstract
The use of a fourth order loop filter within a Continuous-Time (CT) ΔΣ Analog-to-Digital Converter (ADC) structure is explored and a custom prototype in a 0.18μm CMOS with a measured performance of 40dB gain, 70 degree phase margin and unity gain bandwidth of 79.060 MHz which consuming low power consumption at 1.8V power supply. A key innovation is the explicit use of the loop filter output to avoid the signal distortion that had severely limited the performance of ΔΣ ADC's. The proposed architecture consists of the loop filter using active RC integrators in a low power. This study is implemented in Tanner Tools by using 0.18μm CMOS process.
Keywords
Analog to Digital Converter (ADC), Operational Amplifier (OPAMP), Resistor Capacitor (RC) Integrator.
